This invention relates to a small semiconductor device having external terminals electrically connected to a semiconductor element, and to a mounted semiconductor device structure made by mounting this semiconductor device to a printed circuit board.
In recent years, as portable terminals have spread and accompanying reduction in the size and weight of various appliances using semiconductor devices has progressed, the development of semiconductor devices to facilitate this size reduction has become necessary.
In this connection, there is technology which aims to make the size of a semiconductor device approach the size of the semiconductor element on which it is based. A semiconductor device package based on this kind of technology is generally called A-CSP (Chip Size Package, or Chip Scale Package). In a typical CSP structure, metal bumps are disposed within the area of the face of the semiconductor element, and the semiconductor element is-mounted to a printed circuit board by way of these metal bumps. Solder is the material most commonly used for the metal bumps.
In a mounted semiconductor device structure made by mounting a CSP to a board like this, when a temperature change is applied, due to a linear expansion coefficient differential between the semiconductor element and the board, differential thermal expansion arises. Consequently, a thermal distortion occurs repeatedly in the solder bumps sandwiched between the semiconductor element and the board, and the solder bumps may suffer fatigue failure. Accordingly, securing a long life for solder connections in temperature cycle tests is an issue. As an example of a CSP in related art designed with the life of its solder parts in mind, in International Patent Publication No. 504408/1994 there is disclosed a CSP of a structure wherein a tape carrying external terminals is set on a cushion material (an elastomer resin) on the face of a semiconductor element on which a circuit is formed, and the external terminals are electrically connected to the electrodes of the semiconductor element. Because the soft elastomer resin deforms and absorbs thermal distortions, distortions arising in the solder bumps are reduced and their life is increased.
In Japanese Patent Laid-Open No. 224259/1994, a structure is disclosed wherein a semiconductor element is mounted on a ceramic board provided with through holes; electrodes are provided on the other side of the ceramic board; and this is mounted to a printed circuit board. In order to connect the semiconductor device to the printed circuit board via a ceramic board, since the structure reduces the area of electrodes for wire bonding around the semiconductor, the semiconductor package can become reduced in size.
Numerous semiconductor elements are formed at once on a single wafer, and each of the CSP examples above is based on the premise that individual semiconductor elements are processed after being cut from the wafer.
In recent years, technology has been developed for fabricating small semiconductor devices of the same size as their semiconductor elements at a lower cost by carrying out packaging operations on a plurality of semiconductor elements that are still in the wafer.
An example of a CSP which can be fabricated while still in the wafer state is proposed in Nikkei Micro Devices, April 1998: xe2x80x9cNew Method for Cheaply Making Promising Candidate CSP for Chip Size Mountingxe2x80x9d (page 164 to page 167). In the semiconductor device discussed in this article, further interconnections are formed on the semiconductor element; metal via posts of height about 100 xcexcm in height are formed on these interconnections; the space around the via posts is sealed with resin; and metal bumps are formed on the upper faces of the via posts with a barrier metal layer therebetween. A temporary film is spread on the face of via posts in a metallic mold in a process of sealing with resin, so the metallic mold can be removed easily from the sealing resin after pouring into the mold.
In a semiconductor device disclosed in Japanese Patent Laid-open No. 54649/1999, a low elastic modulus layer is formed on the main face of the semiconductor element with an opening over an electrode region where element electrodes are disposed; lands to constitute external electrodes are formed on the low elastic modulus layer; a metal interconnection pattern in which pads on the element electrodes are integrated with the lands and metal interconnections connecting them together is constructed; the surface is covered with solder resist; openings are formed above the lands, and metal balls are joined to the lands.
In this construction, thermal stresses can be absorbed by deformation of the low elastic modulus layer. And because the edges of the opening in the low elastic modulus layer are worked to sloping face shapes, stress concentrations in the metal interconnections are avoided and breakages are prevented.
Also, a passivation film for protecting the semiconductor element may be further provided in a region of the main face of the semiconductor element, excluding the pads. With this related art technology, it is considered that, if a modulus layer is used which is sufficiently low in elastic, modulus and sufficiently thick, the stress-moderating effect is higher than that of the structure described above using sealing resin.
In Japanese Patent Laid-Open No. 204560/1999 there is mentioned a structure wherein, in addition to the structure described above, a resin layer having a linear expansion coefficient between the linear expansion coefficients of the semiconductor element and the low elastic modulus layer is interposed between the two to prevent detachment from each other.
However, in the related art semiconductor devices described above, the following problems may arise.
In the related art semiconductor device discussed above, stresses caused by differential thermal expansion between the semiconductor element and the board on which it is mounted are absorbed by elastic deformation of a low elastic modulus layer; however, to secure sufficient reliability of the metal bumps by this method, it is likely that it will be necessary to make the low elastic modulus layer considerably thick.
In a related art semiconductor device above, a thickness of 10 to 150 xcexcm is considered desirable. And, the opening is formed after the low elastic modulus layer is first formed flat, and exposed, for example, by using scattered light so that the side faces of the opening are not vertical, but rather are sloping.
However, when this kind of process is carried out on a thick film of, for example, a thickness of 100 xcexcm or more, to control the shape of the side faces and to control the bottom end of the opening to dimensions close to the edge of a fine element electrode requires extremely high-precision working technology.
When considered to be semiconductor devices are manufactured on in the related art, at the stage of forming the thick low elastic modulus layer over the entire face of the wafer, the wafer warps severely. As a result, carrying out the highly precise working mentioned above on all of the chips on the warped wafer-is difficult.
Also, as another issue, in a CSP fabricated at the wafer level, there is the problem of its electrical characteristics. That is, when manufacturing a CSP at the wafer level, as a result of problems such as warping of the wafer, it is difficult to form a very thick resin layer, and the insulating layer interposed between the interconnections of the package and the semiconductor element tend to become thin, and the interconnection capacitance tends to become large.
When the interconnection capacitance becomes large, severe noise arises in the signal lines, and there is a risk of the device malfunctioning. Consequently, securing the thickness of the insulating film between the package interconnections and the semiconductor element surface becomes an issue.
The technology set forth in Japanese Patent Laid-Open No. 204560/1999 relates to a semiconductor device wherein a resin layer is interposed between a semiconductor chip and a low elastic modulus layer. Here, because the differences in the elastic modulus and the linear expansion coefficients of the semiconductor chip and the low elastic modulus layer are large, to prevent stresses concentrating at the interface between the two and cracking or detachment consequently occurring, a resin film leaving an elastic modulus and a linear expansion coefficient between those of the semiconductor chip and the low elastic modulus layer is interposed between them.
The resin film in the semiconductor device set forth in Japanese Patent Laid-Open No. 204560/1999; formed between a semiconductor chip and the low elastic modulus layer, the detail of the opening is not disclosed. The resin film has an opening in a region where element electrodes are disposed, and because the edge of that opening is in substantially the same position as or in a position further away than the edge of the opening in the low elastic modulus layer as seen from the center of an element electrode, interconnections are formed directly on the passivation film around the element electrodes.
When interconnections are formed directly on the passivation film like this, because the passivation film is an inorganic film which is difficult to make thick, the static capacitance between the interconnections and the passivation film is large.
In this case, when in the future the operation of semiconductor devices has become faster, there is a risk of the static capacitance between the interconnections and the passivation film causing the device to malfunction.
In this related art semiconductor device, at the periphery of the device, the semiconductor element edge and the edges of the low elastic modulus layer and the solder resist all coincide. Consequently, when this semiconductor device is fabricated at the wafer level, in the final dicing of the wafer into individual semiconductor devices, the resin film and the semiconductor element, whose hardnesses differ greatly, are cut simultaneously. When this happens, there is a risk of the resin film and the semiconductor element suffering damage at their interface. This leads to the possibility of cracking occurring in the semiconductor element and detachment occurring at the interface.
It is therefore an object of the present invention to solve the problems described above and to realize a semiconductor device which is highly reliable, has superior electrical characteristics, and which can be manufactured at the wafer level, and to realize a mounted semiconductor device structure including this semiconductor device.
To achieve this object and other objects, the invention provides the following basic constructions.
(1) A semiconductor device having a semiconductor element, including: element electrodes formed on the semiconductor element surface; a passivation film formed on the semiconductor element surface and having openings above the element electrodes; conducting lands for external terminals to be joined to; a stress-moderating layer interposed between the passivation film and the lands, and having an opening above the element electrodes with its edges forming sloping faces; an insulating film interposed between the passivation film and the stress moderating layer, and having openings above the element electrodes; conducting interconnections electrically connecting the element electrodes with the lands; a surface protection film formed at the ultimate surface of the semiconductor device and having openings above the lands; and external terminals joined to the lands, wherein the distances from the centers of the element electrodes to the edges of the openings formed in the passivation film, the insulating film, and the stress-moderating layer increase in the order of the insulating film, the passivation film, and the stress-moderating layer.
(2) Preferably, in (1) above, at the peripheral sides of the semiconductor device, the edges of the insulating film, the stress-moderating layer, and the surface protection film are all formed inside the edge of the semiconductor element.
(3) And preferably, in (1) or (2) above, the surface protection film is thicker at the element electrodes, where the stress-moderating layer is not present, than on the flat part of-the stress-moderating layer.
(4) And preferably, in (1) to (3) above, the element electrodes include a power supply pad, a ground pad. Also, a signal pad, and a power supply interconnection and a ground interconnection led out from the power supply pad and the ground pad are thicker than a signal interconnection led out from the signal pad.
(5) A mounted semiconductor device structure made by mounting a semiconductor device, according to any one of (1) through (4) by way of the external terminals, to a printed circuit board having conducting lands for the external terminals to be joined to, conducting interconnections interconnecting the lands, and a surface protection film formed at the ultimate surface of the printed circuit board with openings above the lands.
(6) A mounted semiconductor device structure made by mounting a semiconductor device having at least a semiconductor element, conducting lands for electrically connecting the semiconductor element to the outside, a surface protection film formed at the ultimate surface of the semiconductor device with openings above the lands, and external terminals joined to the lands by way of the external terminals to a printed circuit board having at least conducting lands for joining external electrodes to, and a surface protection film having openings above these lands. On the semiconductor device side, the openings in the surface protection film are formed inside the edges of the lands. On the printed circuit board side, the lands are formed inside the edges of the openings in the surface protection film. The diameter of the lands on the printed circuit board side is smaller than the diameter of the openings in the surface protection film on the semiconductor device side.
(7) Preferably, in (5) above, on the semiconductor device side, the openings in the surface protection film are formed inside the edges of the lands, and on the printed circuit board side the lands are formed inside the edges of the openings in the surface protection film, and the diameter of the lands on the printed circuit board side is smaller than the diameter of the openings in the surf ace protection film on the semiconductor device side.
(8) A mounted semiconductor device structure made by mounting a plurality of semiconductor devices, each according to any one of (1) to (4) above to a printed circuit board according to (5) above.
(9) A mounted semiconductor device structure made by mounting a plurality of semiconductor devices, each according to any one of (1) to (4) above, to a printed circuit board according to (7) above.
In a semiconductor device according to the invention, the passivation film is an inorganic film of sin or SiO2 formed to protect the semiconductor element, and its thickness is 1 xcexcm at the most.
The thick stress-moderating layer is formed to a thickness of 40 xcexcm or more using a low elastic modulus resin material having a modulus of longitudinal elasticity of 2000 MPa or less. Because distortions caused by differential thermal expansion between the semiconductor element and the printed circuit board, when the semiconductor device is mounted to a printed circuit board, are absorbed by this stress-moderating layer, distortions arising in the external terminals are reduced and high reliability is realized.
The stress-moderating layer is formed by being applied to parts other than the element electrodes using a printing method. Because the openings are already forming at the application stage, the step of removing material to make the opening is not necessary and consequently the above-mentioned problem that it is difficult to work a warped wafer does not arise.
Also, the edges of the opening in the applied stress-moderating layer flow and form gently sloping faces. As a result of the edges forming sloping faces, even if the stress-moderating layer is thick, forming interconnections over its step is easy and stress concentrations at the parts of interconnections formed over the step parts are reduced and the reliability of the interconnections is high.
On the other hand, because at the parts where the edges flow to form sloping faces the distances are relatively large, controlling the dimensions of the opening with high precision is difficult. To make the opening over the element electrodes with certainty, it is necessary to form the edges of the opening in the stress-moderating layer in positions well away from the element electrodes.
At this time, when the stress-moderating layer is not formed in the vicinity of the element electrodes, but instead near the feet of the sloping faces of the stress-moderating layer, because the distance between the interconnections and the semiconductor element surface is small, there is a risk of the static capacitance of interconnections at these locations being large.
To avoid this, in this invention, an insulating film interposed between the stress-moderating layer and the passivation film is formed, and by this insulating film being interposed between the interconnections and the semiconductor element surface, even in the vicinities of the element electrodes, increased interconnection capacitance is prevented and a semiconductor device having superior electrical characteristics is realized.
The thickness of the insulating film is adjusted to suit the electrical characteristics required of the semiconductor device, and is made about 3 to 20 xcexcm. Over the element electrodes, the openings in the insulating film are formed inside the openings in the passivation film.
As a result, interconnections led out from the element electrodes immediately pass up onto the insulating film, without passing over the passivation film, and this is advantageous to the electrical characteristics of the device. Also, when the openings in the passivation film are formed on the inside, because the edges of the passivation film project beyond the edges of the insulating film, stress concentrations arise in the interconnections at these parts, and there is a risk of the interconnections breaking. And, because it is necessary to form openings above fine element electrodes, a high-precision method such as photolithography, for example, is used for the openings in the insulating film.
The insulating film in the semiconductor device of this invention is interposed between the interconnections near the element electrodes and the semiconductor element surface, and is formed to reduce the static capacitance of the interconnections.
The semiconductor device of this invention can be manufactured at the wafer level, and can be manufactured by the following process, for example.
That is, the present invention relates to a structure of a small semiconductor device which can be manufactured while still in the wafer state, wherein by interposing a thick stress-moderating layer with a low elastic modulus between a semiconductor element and interconnections and lands, it is possible to absorb distortions caused by differential thermal expansion between the semiconductor element and a printed circuit board in temperature cycles, and thereby improve the reliability of external terminals and also improve the electrical performance of the device by reducing static capacitances between interconnections inside the semiconductor element and other interconnections of the device.
In addition, by virtue of an insulating film being interposed between interconnections and the semiconductor element, around the element electrodes, where the stress-moderating layer is not formed, the, static capacitance of these parts is also reduced.
On the surface of a wafer on which numerous semiconductor elements have been formed, a passivation film with openings over element electrodes is formed. On this passivation film, first, a light-sensitive resin material which is to become an insulating film, is applied to the wafer face by spin coating, and openings are formed in this over the element electrodes by photolithography.
Then, a resin material to become a stress-moderating layer is applied to the wafer face by printing. A screen mask used during the printing has a pattern masking the region where the element electrodes are formed, and an opening is formed in this element electrode formation region simultaneously with the printing. After being left to stand until the edges of the stress-moderating layer have flowed and become sloping faces, the wafer is dried.
Next, lands on the stress-moderating layer and interconnections connecting the element electrodes to the lands are formed en bloc on the wafer face using thin film processes as follows: A metal film is formed on the wafer face by sputtering; photoresist is applied to this by spin coating; a pattern of openings for interconnections and lands is formed in this by photolithography; interconnections and lands are formed by electroplating with this resist pattern as a guide; the photoresist is removed; and the metal film is removed by etching to leave plated parts constituting interconnections and lands.
Then, a light-sensitive resin material to become a surface protection film is formed on the wafer face by, for example, spin coating or printing, and openings are formed in it over the lands by photolithography. Solder balls are then deposited in the openings over the lands using a mask, and are joined to the lands by reflowing. Finally, the wafer is diced into individual semiconductor devices.
When a semiconductor device, according to the invention, is made by wafer processes like this, finally the wafer must be cut up with a dicer to separate the individual semiconductor devices. And when resin layers such as the insulating film, the stress-moderating layer, and the surface protection film are present on the lines to be cut with a cutter (called scribe lines), resin films and the semiconductor element, which have greatly different hardnesses, are cut at the same time. When this happens, there is a risk of detachment occurring at the interface between the resin films and the semiconductor element, and of damage such as cracking of the semiconductor element occurring near the interface.
To avoid this, in the semiconductor device of this invention, preferably, the edges of the semiconductor device, the edges of the insulating film, the stress-moderating layer and the surface protection film are all formed inside the edges of the semiconductor element. When this is done, no resin film is present in the scribe area and damage that can occur during dicing can be reduced.
In the semiconductor device of the present invention, because the main surface of the semiconductor element is covered with a thick stress-moderating layer, xcex1-rays produced by the solder bumps and light entering from outside, which both can be causes of the semiconductor device malfunctioning, are blocked, and the semiconductor device is highly reliable with respect to xcex1-rays and light.
However, because the stress-moderating layer is not present in the element electrode formation region, the incursion of xcex1-rays and light is potentially an issue. In the semiconductor device of this invention, because an insulating film is formed in the element electrode formation region, xcex1-rays and light are blocked to some extent by this insulating film.
However, when the thickness of the insulating film is insufficient, preferably, the thickness of the surface protection film is made greater in the element electrode formation region than it is over the flat part of the stress-moderating layer, thereby providing a combined thickness of the insulating film and the surface protection film sufficient to block xcex1-rays and light.
By means of the construction described above, it is possible to secure reliability of the external terminals and realize a semiconductor device which also has excellent electrical characteristics and resistance to xcex1-rays and light, and which can be fabricated en bloc at the wafer level at low cost.
Finally, in a mounted semiconductor device structure made by mounting a semiconductor device according to the invention to a printed circuit board, by adopting a structure wherein lands on the printed circuit board side project into the external terminals and making these lands small in diameter, it is possible to further improve the reliability of the external terminals and to make the pitch of the external terminals narrow.